This invention relates to a network apparatus.
Reduction of power consumption is demanded of a network apparatus. There has been particularly studied a method of cutting excessive power consumption by controlling the performance of the network apparatus to the one, which is sufficient for transfer performance.
JP 2009-111707 A and JP 2011-250237 A are given as background art of a technical filed to which this invention belongs.
JP 2009-111707 A discloses a packet transfer apparatus that includes a header processing part. The header processing part includes a plurality of packet processing circuits for executing packet processing. A circuit count determining circuit determines whether or not a packet processing circuit is in operation by monitoring the count of lines, over which communication is held, and the volume of traffic input from the lines. Based on the results of this determination, power supply and clocks are shut off for packet processing circuits that are not needed, thereby realizing power saving of the packet transfer apparatus.
In order to reduce power consumption depending on performance in this manner, required performance needs to be predicted/estimated precisely. This is because insufficient performance deteriorates communication quality by causing a packet loss, aggravating delay, and the like. JP 2011-250237 A discloses a method involving controlling the operation of a plurality of packet processing circuits that are included in a packet transfer apparatus. The method disclosed in JP 2011-250237 A includes a first step of accumulating packet information history of packets that are input to and output from the packet transfer apparatus in unit time, a second step of calculating an input band of packets that are input to the packet transfer apparatus per unit time based on the packet information history, a third step of calculating the count of packets that are accumulated in a queue of the packet transfer apparatus per unit time based on the packet information history, a fourth step of setting processing performance control information for packet processing circuits that are allowed to operate depending on the input band per unit time and the packet count per unit time, and a fifth step of controlling the operation of the plurality of packet processing circuits based on the set control information.